A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions

Yusaku KANETA  Shingo YOSHIZAWA  Shin-ichi MINATO  Hiroki ARIMURA  Yoshikazu MIYANAGA  

IEICE TRANSACTIONS on Information and Systems   Vol.E95-D   No.7   pp.1847-1857
Publication Date: 2012/07/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E95.D.1847
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
FPGA,  string matching,  regular expression matching,  bit-parallel algorithm,  event stream processing,  

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In this paper, we propose a novel architecture for large-scale regular expression matching, called dynamically reconfigurable bit-parallel NFA architecture (Dynamic BP-NFA), which allows dynamic loading of regular expressions on-the-fly as well as efficient pattern matching for fast data streams. This is the first dynamically reconfigurable hardware with guaranteed performance for the class of extended patterns, which is a subclass of regular expressions consisting of union of characters and its repeat. This class allows operators such as character classes, gaps, optional characters, and bounded and unbounded repeats of character classes. The key to our architecture is the use of bit-parallel pattern matching approach, in which the information of an input non-deterministic finite automaton (NFA) is first compactly encoded in bit-masks stored in a collection of registers and block RAMs. Then, the NFA is efficiently simulated by a fixed circuitry using bitwise Boolean and arithmetic operations consuming one input character per clock regardless of the actual contents of an input text. Experimental results showed that our hardwares for both string and extended patterns were comparable to previous dynamically reconfigurable hardwares in their performances.