A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms

Shuangqu HUANG  Xiaoyang ZENG  Yun CHEN  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E95-D   No.2   pp.403-412
Publication Date: 2012/02/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E95.D.403
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
iterative decoding,  LDPC codes,  reconfigurable architecture,  TDMP,  TPMP,  

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Summary: 
In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.