A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks

Masatoshi NAKAMURA  Masato INAGI  Kazuya TANIGAWA  Tetsuo HIRONAKA  Masayuki SATO  Takashi ISHIGURO  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E95-D   No.2   pp.324-334
Publication Date: 2012/02/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E95.D.324
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
reconfigurable device,  physical design,  placement,  routing,  MPLD,  FPGA,  EDA,  

Full Text: PDF(1.7MB)>>
Buy this Article




Summary: 
In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.