An Easily Testable Routing Architecture and Prototype Chip

Kazuki INOUE  Masahiro KOGA  Motoki AMAGASAKI  Masahiro IIDA  Yoshinobu ICHIDA  Mitsuro SAJI  Jun IIDA  Toshinori SUEYOSHI  

IEICE TRANSACTIONS on Information and Systems   Vol.E95-D    No.2    pp.303-313
Publication Date: 2012/02/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E95.D.303
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
design for testability,  homogeneous architecture,  test method,  prototype chip,  

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Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture.

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