A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy

Chao YAN  Hongjun DAI  Tianzhou CHEN  

IEICE TRANSACTIONS on Information and Systems   Vol.E95-D   No.1   pp.38-45
Publication Date: 2012/01/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E95.D.38
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Trust, Security and Privacy in Computing and Communication Systems)
Category: Trust
soft errors,  fault tolerance,  double execution,  instruction reuse buffer,  fast error correcting code,  

Full Text: PDF>>
Buy this Article

Soft error has become an increasingly significant concern in modern micro-processor design, it is reported that the instruction-level temporal redundancy in out-of-order cores suffers an performance degradation up to 45%. In this work, we propose a fault tolerant architecture with fast error correcting codes (such as the two-dimensional code) based on double execution. Experimental results show that our scheme can gain back IPC loss between 9.1% and 10.2%, with an average around 9.2% compared with the conventional double execution architecture.