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Design and Implementation of a Handshake Join Architecture on FPGA
Yasin OGE Takefumi MIYOSHI Hideyuki KAWASHIMA Tsutomu YOSHINAGA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Online ISSN: 1745-1361
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer Architecture
FPGA, data stream processing, window join operator, accelerator, handshake join,
Full Text: PDF(675.4KB)>>
A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.