IEICE Trans - Design and Implementation of a Handshake Join Architecture on FPGA

Design and Implementation of a Handshake Join Architecture on FPGA

Yasin OGE  Takefumi MIYOSHI  Hideyuki KAWASHIMA  Tsutomu YOSHINAGA

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E95-D    No.12    pp.2919-2927
Publication Date: 2012/12/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E95.D.2919
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer Architecture
Keyword:
FPGA,  data stream processing,  window join operator,  accelerator,  handshake join,

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Summary:
A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.