Low Power Clock Gating for Shift Register

Ki-Sung SOHN  Da-In HAN  Ki-Ju BAEK  Nam-Soo KIM  Yeong-Seuk KIM  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.8   pp.1447-1448
Publication Date: 2012/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.1447
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
Keyword: 
low power,  small area,  clock gating circuit,  

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Summary: 
A new clock gating circuit suitable for shift register is presented. The proposed clock gating circuit that consists of basic NOR gates is low power and small area. The power consumption of a 16-bit shift register implemented with the proposed clock gating circuit is about 66% lower than that found when using the conventional design.