Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates

Zhengfan XIA  Shota ISHIHARA  Masanori HARIYAMA  Michitaka KAMEYAMA  

IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.8   pp.1434-1443
Publication Date: 2012/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.1434
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
asynchronous pipeline,  dual-rail,  critical datapath,  

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This paper introduces a novel design method of an asynchronous pipeline based on dual-rail dynamic logic. The overhead of handshake control logic is greatly reduced by constructing a reliable critical datapath, which offers the pipeline high throughput as well as low power consumption. Synchronizing Logic Gates (SLGs), which have no data dependency problem, are used in the design to construct the reliable critical datapath. The design targets latch-free and extremely fine-grain or gate-level pipeline, where the depth of every pipeline stage is only one dual-rail dynamic logic. HSPICE simulation results, in a 65 nm design technology, indicate that the proposed design increases the throughput by 120% and decreases the power consumption by 54% compared with PS0, a classic dual-rail asynchronous pipeline implementation style, in 4-bit wide FIFOs. Moreover, this method is applied to design an array style multiplier. It shows that the proposed design reduces power by 37.9% compared to classic synchronous design when the workloads are 55%. A chip has been fabricated with a 44 multiplier function, which works well at 2.16G data-set/s (Post-layout simulation).