Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm

Yuli ZHANG  Jun HAN  Xinqian WENG  Zhongzhu HE  Xiaoyang ZENG  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.8   pp.1415-1426
Publication Date: 2012/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.1415
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
SHA-3,  BLAKE algorithm,  ISE,  ASIP,  

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Summary: 
This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335 Mbps and 176 Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.