For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF)
Xiayu LI Song JIA Limin LIU Yuan WANG
IEICE TRANSACTIONS on Electronics
Publication Date: 2012/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
flip-flop, pulse generator free, high speed, low power,
Full Text: PDF(255.4KB)>>
A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.