A 1-V TSPC Dual Modulus Prescaler with Speed Scalability Using Forward Body Biasing in 0.18 µm CMOS

Hyunchol SHIN  

IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.6   pp.1121-1124
Publication Date: 2012/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.1121
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
CMOS,  prescaler,  forward body bias,  extended true single phase clock logic,  

Full Text: PDF(2.2MB)>>
Buy this Article

The operating speed scalability is demonstrated by using the forward body biasing method for a 1-V 0.18-µm CMOS true single-phase clocking (TSPC) dual-modulus prescaler. With the forward body bias voltage varying between 0 and 0.4 V, the maximum operating speed changes by about 40–50% and the maximum input sensitivity frequency changes by about 400%. This speed scalability is achieved with less than 0.5-dB phase noise degradation. This demonstration indicates that the forward body biasing method is instrumental to build a cost-saving power-efficient 1-V 0.18-µm CMOS radio for low-power WBAN and WSN applications.