Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit

Kosuke KATAYAMA  Mizuki MOTOYOSHI  Kyoya TAKANO  Ryuichi FUJIMOTO  Minoru FUJISHIMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.6   pp.1077-1085
Publication Date: 2012/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.1077
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
parameter extraction,  MOSFET modeling,  millimeter wave,  

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Summary: 
In this paper, we propose a new method for the bias-dependent parameter extraction of a MOSFET, which covers DC to over 100 GHz. The DC MOSFET model provided by the chip foundry is assumed to be correct, and the core DC characteristics are designed to be asymptotically recovered at low frequencies. This is carried out by representing the corrections required at high frequencies using a bias-dependent Y matrix, assuming that a parasitic nonlinear two-port matrix (Y-wrapper) is connected in parallel with the core MOSFET. The Y-wrapper can also handle the nonreciprocity of the parasitic components, that is, the asymmetry of the Y matrix. The reliability of the Y-wrapper model is confirmed through the simulation and measurement of a one-stage common-source amplifier operating at several bias points. This paper will not discuss about non-linearity.