A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter

Daisuke MIYASHITA  Hiroyuki KOBAYASHI  Jun DEGUCHI  Shouhei KOUSAI  Mototsugu HAMADA  Ryuichi FUJIMOTO  

IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.6   pp.1008-1016
Publication Date: 2012/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.1008
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
ADPLL,  TDC,  phase interpolator,  phase noise,  

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This paper presents an ADPLL using a hierarchical TDC composed of a 4fLO DCO followed by a divide-by-4 circuit and three stages of known phase interpolators. We derived simple design requirements for ensuring precision of the phase interpolator. The proposed architecture provides immunity to PVT and local variations, which allows calibration-free operation, as well as sub-inverter delay resolution contributing to good in-band phase noise performance. Also the hierarchical TDC makes it possible to employ a selective activation scheme for power saving. Measured performances demonstrate the above advantages and the in-band phase noise reaches -104 dBc/Hz. It is fabricated in a 65 nm CMOS process and the active area is 0.18 mm2.