Improvement of Address Discharge Delay Time Using Modified Reset Waveform in AC Plasma Display Panel

Bhum Jae SHIN  Hyung Dal PARK  Heung-Sik TAE  

IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.5   pp.958-963
Publication Date: 2012/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.958
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Displays
selective reset waveform,  address-on-time,  wall voltage variation,  address discharge delay time,  Vt closed curves analysis,  

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In order to improve the address discharge characteristics, we propose the modified selective reset waveform utilizing the address-bias voltage (Va-bias) during the ramp-up period. It is revealed that the proper Va-bias makes the weak discharge between the address and scan electrodes which plays a role in sufficiently removing the wall charge, thereby contributing to minimizing the wall-voltage variation during the address-period. As a result of adopting the Va-bias in the conventional selective reset driving waveform, it was found that the address discharge delay time can be shortened by approximately 40 ns and the address period of each subfield can be significantly reduced by about 43 µs.