Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations

Amir FATHI  Sarkis AZIZIAN  Khayrollah HADIDI  Abdollah KHOEI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.4   pp.706-709
Publication Date: 2012/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.706
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: 
Keyword: 
Modified Booth Algorithm,  high speed,  

Full Text: PDF>>
Buy this Article




Summary: 
This paper presents design of a novel high speed booth encoder-decoder in a 0.35 µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.