A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology

Tetsuya IIZUKA  Satoshi MIURA  Ryota YAMAMOTO  Yutaka CHIBA  Shunichi KUBO  Kunihiro ASADA  

IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.4   pp.661-667
Publication Date: 2012/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.661
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
time-to-digital converter,  pulse shrinking,  buffer ring,  

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This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9 bit, 580 fs resolution in a 0.18 µm CMOS technology with 0.04 mm2 area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5 MS/s ranges from 10.8 to 12.6 mW depending on the input time intervals.