On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction

Jinmyoung KIM
Toru NAKURA
Hidehiro TAKATA
Koichiro ISHIBASHI
Makoto IKEDA
Kunihiro ASADA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E95-C    No.4    pp.643-650
Publication Date: 2012/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.643
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
resonant supply noise,  switched parasitic capacitors,  sleep block,  power gating,  

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Summary: 
Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2 V, 65 nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130 MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.