Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays

Akira KOTABE  Riichiro TAKEMURA  Yoshimitsu YANAGAWA  Tomonori SEKIGUCHI  Kiyoo ITOH  

IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.4   pp.594-599
Publication Date: 2012/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.594
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
DRAM,  low voltage,  sense amplifier,  mid-point sensing,  

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A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-VT PMOS amplifier and a low-VT NMOS amplifier which is composed of high-VT NMOSs and a low-VT cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-VT CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-VT NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.