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Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor
Kousuke MIYAJI Kentaro HONDA Shuhei TANAKAMARU Shinji MIYANO Ken TAKEUCHI
IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
6T/8T-SRAM, asymmetric pass gate transistor, local electron injection, disturb/write margin, read speed,
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Three types of electron injection scheme: both side injection scheme and self-repair one side injection scheme Type A (injection for once) and Type B (injection for twice) are proposed and analyzed comprehensively for 65 nm technology node 6T- and 8T-SRAM cells to find the optimum injection scheme and cell architecture. It is found that the read speed degrades by as much as 6.3 times in the 6T-SRAM with the local injected electrons. However, the read speed of the 8T-SRAM cell does not degrade because the read port is separated from the write pass gate transistors. Furthermore, the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb and write characteristics. The worst cell characteristics of Type A and Type B self-repair one side injection schemes were found to be the same. In the self-repair one side injection 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed schemes have no process or area penalty compared with the standard CMOS-process.