Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips

Wei ZHONG  Takeshi YOSHIMURA  Bei YU  Song CHEN  Sheqin DONG  Satoshi GOTO  

IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.4   pp.534-545
Publication Date: 2012/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.534
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
networks on chip (NoC),  placement,  synthesis,  topology,  

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Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27.54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.