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Design of Predistorter with Efficient Updating Algorithm of Power Amplifier with Memory Effect
Yasuyuki OISHI Shigekazu KIMURA Eisuke FUKUDA Takeshi TAKANO Daisuke TAKAGO Yoshimasa DAIDO Kiyomichi ARAKI
Publication
IEICE TRANSACTIONS on Electronics
Vol.E95C
No.3
pp.382394 Publication Date: 2012/03/01 Online ISSN: 17451353
DOI: 10.1587/transele.E95.C.382 Print ISSN: 09168516 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: power amplifier, IMD measurement, memory effect, bias impedance, predistorter,
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Summary:
This paper describes a method to design a predistorter (PD) for a GaNFET power amplifier (PA) by using nonlinear parameters extracted from measured IMD which has asymmetrical peaks peculiar to a memory effect with a secondorder lag. While, computationally efficient equations have been reported by C. Rey et al. for the memory effect with a firstorder lag. Their equations are extended to be applicable to the memory effect with the secondorder lag. The extension provides a recursive algorithm for cancellation signals of the PD each of which updating is made by using signals in only two sampling points. The algorithm is equivalent to a memory depth of two in computational efficiency. The required times for multiplications and additions are counted for the updating of all the cancellation signals and it is confirmed that the algorithm reduces computational intensity lower than half of a memory polynomial in recent papers. A computer simulation has clarified that the PD improves the adjacent channel leakage power ratio (ACLR) of OFDM signals with several hundred subcarriers corresponding to 4G mobile radio communications. It has been confirmed that a fifthorder PD is effective up to a higher power level close to 1 dB compression. The improvement of error vector magnitude (EVM) by the PD is also simulated for OFDM signals of which the subcarrier channels are modulated by 16 QAM.

