Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

Yoshitaka HIRAMATSU  Hasitha Muthumala WAIDYASOORIYA  Masanori HARIYAMA  Toru NOJIRI  Kunio UCHIYAMA  Michitaka KAMEYAMA  

IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.12   pp.1872-1882
Publication Date: 2012/12/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.1872
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
block matching,  heterogeneous multi-core,  dynamically reconfigurable processor,  data transfer,  accelerator,  

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The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15 ms for a VGA image with 1616 pixel blocks.