TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC

Hung Viet NGUYEN  Myunghwan RYU  Youngmin KIM  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.12   pp.1864-1871
Publication Date: 2012/12/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.1864
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
3D IC,  TSV (Through Silicon Via),  power,  delay,  optimization,  interconnect,  repeater,  

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Summary: 
This paper evaluates the impact of Through-Silicon Via (TSV) on the performance and power consumption of 3D circuitry. The physical and electrical model of TSV which considers the coupling effects with adjacent TSVs is exploited in our investigation. Simulation results show that the overall performance of 3D IC infused with TSV can be improved noticeably. The frequency of the ring oscillator in 4-tier stacking layout soars up to two times compared with one in 2D planar. Furthermore, TSV process variations are examined by Monte Carlo simulations to figure out the geometrical factor having more impact in manufacturing. An in-depth research on repeater associated with TSV offers a metric to compute the optimization of 3D systems integration in terms of performance and energy dissipation. By such optimization metric with 45 nm MOSFET used in our circuit layout, it is found that the optimal number of tiers in both performance and power consumption approaches 4 since the substantial TSV-TSV coupling effect in the worst case of interference is expected in 3D IC.