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A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing
I-Jen CHAO Chung-Lun HSU Bin-Da LIU Soon-Jyu CHANG Chun-Yueh HUANG Hsin-Wen TING
IEICE TRANSACTIONS on Electronics
Publication Date: 2012/11/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
delta-sigma modulator, DSM, opamp sharing, relaxed dynamic element matching (DEM) timing,
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This paper proposes a third-order low-distortion delta-sigma modulator (DSM). The third-order noise shaping is achieved by a single opamp (excluding the quantizer). In the proposed DSM structure, the timing limitation on the quantizer and dynamic element matching (DEM) logic in a conventional low-distortion structure can be relaxed from a non-overlapping interval to half of the clock period. A cyclic analog-to-digital converter with a loading-free technique is utilized as a quantizer, which shares an opamp with the active adder. The signal transfer function (STF) is preserved as unity, which means that the integrators process only the quantization noise component. As a result, the opamp used for the integrators has lower requirements, as low-distortion DSMs, on slew rate, output swing, and power consumption. The proposed third-order DSM with a 4-bit cyclic-type quantizer is implemented in a 90-nm CMOS process. Under a sampling rate of 80 MHz and oversampling ratio of 16, simulation results show that an 81.97-dB signal-to-noise and distortion ratio and an 80-dB dynamic range are achieved with 4.17-mW total power consumption. The resulting figure of merit (FOM) is 81.5 fJ/conversion-step.