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Balanced Switching Schemes for GradientError Compensation in CurrentSteering DACs
Xueqing LI Qi WEI Fei QIAO Huazhong YANG
Publication
IEICE TRANSACTIONS on Electronics
Vol.E95C
No.11
pp.17901798 Publication Date: 2012/11/01
Online ISSN: 17451353
DOI: 10.1587/transele.E95.C.1790
Print ISSN: 09168516 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: digitaltoanalog converter, gradient errors, nonlinearity, switching scheme, the integral nonlinearity,
Full Text: PDF(3.6MB)>>
Summary:
This paper introduces balanced switching schemes to compensate linear and quadratic gradient errors, in the unary current source array of a currentsteering digitaltoanalog converter (DAC). A novel algorithm is proposed to avoid the accumulation of gradient errors, yielding much less integral nonlinearities (INLs) than conventional switching schemes. Switching scheme examples with different number of current cells are also exhibited in this paper, including symmetric arrays and nonsymmetric arrays in round and square outlines. (a) For symmetric arrays where each cell is divided into two parallel concentric ones, the simulated INL of the proposed round/square switching scheme is less than 25%/40% of conventional switching schemes, respectively. Such improvement is achieved by the cancelation of linear errors and the reduction of accumulated quadratic errors to near the absolute lower bound, using the proposed balanced algorithm. (b) For nonsymmetric arrays, i.e. arrays where cells are not divided into parallel ones, linear errors cannot be canceled, and the accumulated INL varies with different quadratic error distribution centers. In this case, the proposed algorithm strictly controls the accumulation of quadratic gradient errors, and different from the algorithm in symmetric arrays, linear errors are also strictly controlled in two orthogonal directions simultaneously. Therefore, the INLs of the proposed nonsymmetric switching schemes are less than 64% of conventional switching schemes.

