Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects

Mohammad Taghi TEIMOORI  Ali JAHANIAN  Adel DOKHANCHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E95-C   No.10   pp.1610-1619
Publication Date: 2012/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.1610
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Recent Progress in Microwave and Millimeter-Wave Technologies)
Category: 
Keyword: 
microwave on-chip interconnect,  FPGA,  performance,  

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Summary: 
Microwave interconnects have been proposed recently to break-down long wires in large integrated circuits. In this paper, using of coplanar waveguide RF interconnects in FPGAs is explored to improve performance and reduce routing congestion. We propose a new FPGA architecture consisting of both metal wires and RF receivers/transmitters corresponding with an algorithm to route the proposed FPGA. Experimental results show that used routing tracks and routing congestion are reduced by 23.8% and 7.06%, respectively and performance of the attempted benchmarks is improved by about 33% using this technique. These benefits are earned in reasonable cost of area and power consumption which is negligible for large and complex circuits.