Time Slot Assignment Algorithms to Upstream Links for Decreasing Transmission Latency in IEEE 802.16j Networks

Go HASEGAWA  Shinpei TANAKA  Yoshiaki TANIGUCHI  Hirotaka NAKANO  

Publication
IEICE TRANSACTIONS on Communications   Vol.E95-B   No.5   pp.1793-1801
Publication Date: 2012/05/01
Online ISSN: 1745-1345
DOI: 10.1587/transcom.E95.B.1793
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Terrestrial Wireless Communication/Broadcasting Technologies
Keyword: 
IEEE 802.16j,  wireless multihop network,  time division multiple access (TDMA),  time slot,  end-to-end transmission latency,  

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Summary: 
In this paper, the authors focus on upstream transmission in TDMA-based IEEE 802.16j and propose two time slot assignment algorithms to decrease end-to-end transmission latency. One of the proposed algorithms assigns time slots considering the hop count from a gateway node, and the other takes the path from the relay node to the gateway node into account. In addition, a restriction in assigning time slots is introduced to reduce the delay at each relay node. The algorithms with the restriction assign later time slots considering the time slot order of links connecting a relay node. The performance of the proposed algorithms is evaluated through simulation experiments from the viewpoints of frame size and end-to-end transmission latency, and it is confirmed that the proposed algorithms achieve small transmission latency regardless of packet generation rate in the network, and decrease the transmission latency by up to 70% compared with the existing algorithm.