A Memory-Efficient Bit-Split Pattern Matching Architecture Using Shared Match Vectors for Deep Packet Inspection

HyunJin KIM

IEICE TRANSACTIONS on Communications   Vol.E95-B    No.11    pp.3594-3596
Publication Date: 2012/11/01
Online ISSN: 1745-1345
DOI: 10.1587/transcom.E95.B.3594
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Network Management/Operation
computer network security,  deep packet inspection,  finite state machine,  string matching,  network monitoring,  

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This paper proposes a bit-split string matcher architecture for a memory-efficient hardware-based parallel pattern matching engine. In the proposed bit-split string matcher, multiple finite-state machine (FSM) tiles share match vectors to reduce the required number of stored match vectors. By decreasing the memory size for storing match vectors, the total memory requirement can be minimized.