Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process

Shusuke YOSHIMOTO  Takuro AMASHITA  Shunsuke OKUMURA  Koji NII  Masahiko YOSHIMOTO  Hiroshi KAWAGUCHI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E95-A   No.8   pp.1359-1365
Publication Date: 2012/08/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E95.A.1359
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Reliability, Maintainability and Safety Analysis
SRAM,  single-event upset (SEU),  bit error rate (BER),  soft error rate (SER),  neutron particle,  alpha particle,  

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This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/ 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.