A Processor Accelerator for Software Decoding of Reed-Solomon Codes

Kazuhito ITO  Keisuke NASU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E95-A    No.5    pp.884-893
Publication Date: 2012/05/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E95.A.884
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
error correction code,  Reed-Solomon,  accelerator,  decoding,  

Full Text: PDF>>
Buy this Article

Decoding of Reed-Solomon (RS) codes requires many arithmetic operations in the Galois field. While the software decoding of RS codes has the advantage of its flexibility to support RS codes of variable parameters, the speed of the software decoding is slower than dedicated hardware RS decoders because arithmetic operations in the Galois field on an ordinary processor require many instruction steps. To achieve fast software decoding of RS codes, it is effective to accelerate Galois operations by both dedicated circuitry and parallel processing. In this paper, an accelerator is proposed which is attached to the base processor to speed up the software decoding of RS codes by parallel execution of Galois operations.