An Area Efficient Real-Time PFFT Architecture Using Parallel Distributed Arithmetic

Xiaofeng LING  Xinbao GONG  Xiaogang ZANG  Ronghong JIN  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E95-A   No.2   pp.600-603
Publication Date: 2012/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E95.A.600
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Digital Signal Processing
discrete Fourier transform (DFT),  prime factor Fourier transform,  parallel distributed arithmetic,  cyclic convolution,  

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In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.