Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems

Shingo YOSHIZAWA  Yoshikazu MIYANAGA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E95-A   No.2   pp.550-558
Publication Date: 2012/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E95.A.550
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
pipeline FFT processor,  MIMO-OFDM,  VLSI architecture,  IEEE 802.11ac,  

Full Text: PDF(2.3MB)>>
Buy this Article

We present area- and power-efficient pipeline 128- and 128/64-point fast Fourier transform (FFT) processors for 8x8 multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM) systems based on the specification framework of IEEE 802.11ac WLANs. Our new FFT processors use mixed-radix multipath delay commutator (MRMDC) architecture from the point of view of low complexity and high memory use. A conventional MRMDC architecture induces large circuits in delay commutators, which change the order of data sequences for the butterfly units. The proposed architecture replaces delay elements with new commutators that cooperate with other MIMO-OFDM processing blocks. These commutators are inserted in the front and rear of the input and output memory units. Our FFT processors exhibit a 50–51% reduction in logic gates and 70–72% reduction in power dissipation as compared with conventional ones.