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A 24 dB Gain 51–68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors
Ning LI Keigo BUNSEN Naoki TAKAYAMA Qinghong BU Toshihide SUZUKI Masaru SATO Yoichi KAWANO Tatsuya HIROSE Kenichi OKADA Akira MATSUZAWA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/02/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
asymmetric-layout, low noise amplifier, mm-Wave, 60 GHz,
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At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. A four-stage common-source low noise amplifier is implemented in a 65 nm CMOS process. A measured peak power gain of 24 dB is achieved with a power dissipation of 30 mW from a 1.2-V power supply. An 18 dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17 GHz from 51 GHz to 68 GHz, and noise figure (NF) is from 4.0 dB to 7.6 dB.