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A VariabilityAware EnergyMinimization Strategy for Subthreshold Circuits
Junya KAWASHIMA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E95A
No.12
pp.22422250 Publication Date: 2012/12/01 Online ISSN: 17451337
DOI: 10.1587/transfun.E95.A.2242 Print ISSN: 09168508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: subthreshold operation, process variation, minimum operation voltage estimation, energy minimization, yield maximization,
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Summary:
We investigate a design strategy for subthreshold circuits focusing on energyconsumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of lowpower CMOS circuits: (1) The minimum operation voltage (V_{DD}_{min}) of a circuit is dominated by flipflops (FFs), and V_{DD}_{min} of an FF can be improved by upsizing a few key transistors, (2) V_{DD}_{min} of an FF is stochastically modeled by a lognormal distribution, (3) V_{DD}_{min} of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving V_{DD}_{min} may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.

