A Leakage Efficient Instruction TLB Design for Embedded Processors

Zhao LEI  Hui XU  Daisuke IKEBUCHI  Tetsuya SUNATA  Mitaro NAMIKI  Hideharu AMANO  

IEICE TRANSACTIONS on Information and Systems   Vol.E94-D    No.8    pp.1565-1574
Publication Date: 2011/08/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E94.D.1565
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
leakage power,  TLB,  embedded processor,  

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This paper presents a leakage-efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page, the following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage component which holds the recent address-translation information, the TLB access frequency can be drastically decreased, and the instruction TLB can be turned into the low-leakage mode with the dual voltage supply technique. Based on such a design philosophy, three leakage control policies are proposed to maximize the leakage reduction efficiency. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.