A Self-Timed SRAM Design for Average-Case Performance

Je-Hoon LEE  Young-Jun SONG  Sang-Choon KIM  

IEICE TRANSACTIONS on Information and Systems   Vol.E94-D   No.8   pp.1547-1556
Publication Date: 2011/08/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E94.D.1547
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
asynchronous circuit,  SRAM,  self-timed logic,  memory segmentation,  

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This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8 MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.