3D-DCT Processor and Its FPGA Implementation

Yuki IKEGAKI  Toshiaki MIYAZAKI  Stanislav G. SEDUKHIN  

IEICE TRANSACTIONS on Information and Systems   Vol.E94-D   No.7   pp.1409-1418
Publication Date: 2011/07/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E94.D.1409
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
3D-DCT,  array processors,  data manipulation,  FPGA,  

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Conventional array processors randomly access input/coefficient data stored in memory many times during three-dimensional discrete cosine transform (3D-DCT) calculations. This causes a calculation bottleneck. In this paper, a 3D array processor dedicated to 3D-DCT is proposed. The array processor drastically reduces data swapping or replacement during the calculation and thus improves performance. The time complexity of the proposed NNN array processor is O(N) for an N3-size input data cube, and that of the 3D-DCT sequential calculation is O(N4). A specific I/O architecture, throughput-improved architectures, and more scalable architecture are also discussed in terms of practical implementation. Experimental results of implementation on FPGA (field-programmable gate array) suggest that our architecture provides good performance for real-time 3D-DCT calculations.