DSP-Based Parallel Implementation of Speeded-Up Robust Features

Chao LIAO  Guijin WANG  Quan MIAO  Zhiguo WANG  Chenbo SHI  Xinggang LIN  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E94-D   No.4   pp.930-933
Publication Date: 2011/04/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E94.D.930
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Image Recognition, Computer Vision
Keyword: 
digital signal processing,  speeded-up robust features,  SURF,  parallel computing,  image matching,  

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Summary: 
Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.