An H.264/AVC Decoder with Reduced External Memory Access for Motion Compensation

Jaesun KIM  Younghoon KIM  Hyuk-Jae LEE  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E94-D   No.4   pp.798-808
Publication Date: 2011/04/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E94.D.798
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
Keyword: 
H.264/AVC decoder,  motion compensation,  external memory bandwidth,  frame recompression,  

Full Text: PDF(1.4MB)>>
Buy this Article




Summary: 
The excessive memory access required to perform motion compensation when decoding compressed video is one of the main limitations in improving the performance of an H.264/AVC decoder. This paper proposes an H.264/AVC decoder that employs three techniques to reduce external memory access events: efficient distribution of reference frame data, on-chip cache memory, and frame memory recompression. The distribution of reference frame data is optimized to reduce the number of row activations during SDRAM access. The novel cache organization is proposed to simplify tag comparisons and ease the access to consecutive 4×4 blocks. A recompression algorithm is modified to improve compression efficiency by using unused storage space in neighboring blocks as well as the correlation with the neighboring pixels stored in the cache. Experimental results show that the three techniques together reduce external memory access time by an average of 90%, which is 16% better than the improvements achieved by previous work. Efficiency of the frame memory recompression algorithm is improved with a 32×32 cache, resulting in a PSNR improvement of 0.371 dB. The H.264/AVC decoder with the three techniques is fabricated and implemented as an ASIC using 0.18 µm technology.