Low-Overhead Architecture for Security Tag

Ryota SHIOYA  Daewung KIM  Kazuo HORIO  Masahiro GOSHIMA  Shuichi SAKAI  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E94-D   No.1   pp.69-78
Publication Date: 2011/01/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E94.D.69
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
Keyword: 
processor architecture,  tagged architecture,  information security,  information flow tracking,  

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Summary: 
A security-tagged architecture is one that applies tags on data to detect attack or information leakage, tracking data flow. The previous studies using security-tagged architecture mostly focused on how to utilize tags, not how the tags are implemented. A naive implementation of tags simply adds a tag field to every byte of the cache and the memory. Such a technique, however, results in a huge hardware overhead. This paper proposes a low-overhead tagged architecture. We achieve our goal by exploiting some properties of tag, the non-uniformity and the locality of reference. Our design includes the use of uniquely designed multi-level table and various cache-like structures, all contributing to exploit these properties. Under simulation, our method was able to limit the memory overhead to 0.685%, where a naive implementation suffered 12.5% overhead.