F-Scan: A DFT Method for Functional Scan at RTL

Marie Engelene J. OBIEN  Satoshi OHTAKE  Hideo FUJIWARA  

IEICE TRANSACTIONS on Information and Systems   Vol.E94-D   No.1   pp.104-113
Publication Date: 2011/01/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E94.D.104
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Information Network
scan-based DFT,  functional RTL circuits,  high-level testing,  assignment decision diagrams,  

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Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.