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The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop
Zue-Der HUANG Chung-Yu WU
IEICE TRANSACTIONS on Electronics
Publication Date: 2011/08/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
phase-locked loop (PLL), VCO, coupling current-mode injection-locked frequency divider (CCMILFD), SPR-PFD, complementary-type charge pump,
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A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is -69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2 mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.