A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques

Byeong-Woo KOO  Seung-Jae PARK  Gil-Cho AHN  Seung-Hoon LEE  

IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.8   pp.1282-1288
Publication Date: 2011/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1282
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
ADC,  pipeline,  low power,  SHA-free,  circuit sharing,  two-step reference selection,  

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This work describes a 12-bit 100 MS/s 0.13 µm CMOS three-stage pipeline ADC with various circuit design techniques to reduce power and die area. Digitally controlled timing delay and gate-bootstrapping circuits improve the linearity and sampling time mismatch of the SHA-free input network composed of an MDAC and a FLASH ADC. A single two-stage switched op-amp is shared between adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs based on slightly overlapped switching clocks. The interpolation, open-loop offset sampling, and two-step reference selection schemes for a back-end 6-bit flash ADC reduce both power consumption and chip area drastically compared to the conventional 6-bit flash ADCs. The prototype ADC in a 0.13 µm CMOS process demonstrates measured differential and integral non-linearities within 0.44LSB and 1.54LSB, respectively. The ADC shows a maximum SNDR and SFDR of 60.5 dB and 71.2 dB at 100 MS/s, respectively. The ADC with an active die area of 0.92 mm2 consumes 19 mW at 100 MS/s from a 1.0 V supply. The measured FOM is 0.22 pJ/conversion-step.