Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme

Takuya YAGI
Kunihiko USUI
Satoshi UEMORI
Satoshi ITO
Yohei TAN

IEICE TRANSACTIONS on Electronics   Vol.E94-C    No.7    pp.1233-1236
Publication Date: 2011/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1233
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
ADC,  self-calibration,  pipelined ADC,  split ADC,  digitally-assisted analog technology,  

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This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.