For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression
Yongpan LIU Shuangchen LI Jue WANG Beihua YING Huazhong YANG
IEICE TRANSACTIONS on Electronics
Publication Date: 2011/07/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
wireless sensor network, compression accelerator, energy efficient, latency aware, adaptive compression,
Full Text: PDF(1.3MB)>>
This paper proposed a novel platform for sensor nodes to resolve the energy and latency challenges. It consists of a processor, an adaptive compressing module and several compression accelerators. We completed the proposed chip in a 0.18µm HJTC CMOS technology. Compared to the software-based solution, the hardware-assisted compression reduces over 98% energy and 212% latency. Besides, we balanced the energy and latency metric using an adaptive module. According to the scheduling algorithm, the module tunes the state of the compression accelerator, as well as the sampling frequency of the online sensor. For example, given a 9µs constraint for a 1-byte operation, it reduces 34% latency while the energy overheads are less than 5%.