Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Sensor Nodes

Toshishige SHIMAMURA
Shin'ichiro MUTOH
Mitsuru HARADA

IEICE TRANSACTIONS on Electronics   Vol.E94-C    No.7    pp.1206-1211
Publication Date: 2011/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1206
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
sensor node,  power management,  power switch,  energy harvesting,  CMOS,  

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The design and performance of a sub-nanoampere two-stage power management circuit that uses off-chip capacitors for energy accumulation are presented. Focusing on the leakage current and the transition time of the power switch transistor, we estimated the minimum current for accumulating. On the basis of the results, we devised a two-stage power management architecture for sub-nanoampere operation. The simulated and experimental results for the power management circuit describe the accumulating operation with a 1-nA current source.