Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

Li-Rong WANG  Ming-Hsien TU  Shyh-Jye JOU  Chung-Len LEE  

IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.6   pp.1112-1119
Publication Date: 2011/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1112
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
multiplier,  multiply-accumulator,  modified Booth encoding,  reconfigurable,  mixed-Vt,  standard cell library,  

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This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 3232, two 1616 or four 88 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-Vt standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-Vt standard cell library.