IEICE Trans - Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip

Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip

Ryo MINAMI  JeeYoung HONG  Kenichi OKADA  Akira MATSUZAWA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.6   pp.1057-1060
Publication Date: 2011/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1057
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category:
Keyword:
CMOS,  power amplifier,  substrate coupling,  Tx leakage,  mutual coupling,

Full Text: PDF(532.2KB)>>

Summary:
This paper presents measurement of on-chip coupling between PA and LNA integrated on Si CMOS substrate, which is caused by substrate coupling, magnetic coupling, power-line coupling, etc. These components are decomposed by measurements using diced chips. The result reveals that the substrate coupling is the most dominant in CMOS chips and the total isolation becomes less than -50 dB with more than 0.4 mm PA-to-LNA distance.