IEICE Trans - Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit

Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit

Kei MATSUMOTO  Tetsuya HIROSE  Yuji OSAKI  Nobutaka KUROKI  Masahiro NUMA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.6   pp.1042-1048
Publication Date: 2011/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1042
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category:
Keyword:
SRAM,  threshold voltage variation,  compensation circuit,  process variation,  temperature variation,  PVT variation,

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Summary:
We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.